This disclosure relates to flash memory devices and more specifically, to a data I/O circuit of flash memory devices.
In general, a data I/O circuit of a flash memory device includes a page buffer 11, a column select circuit 12, a data line discharge circuit 13 and an sense amplifier circuit 14, as shown in FIG. 1.
The page buffer 11 includes a bit line selector 20, a register circuit 30, switches 40, 60, a data input circuit 50 and a precharge circuit 70. The bit line selector 20 includes NMOS transistors 21 to 24. The register circuit 30 includes a sensing circuit 31 and a latch circuit 32. The data input circuit 50 includes NMOS transistors 51, 52. The switches 40, 60 are each implemented using an NMOS transistor and will be hereinafter referred to as an NMOS transistor. The sources of the NMOS transistors 51, 52 and 60 are all connected to a node D3.
Furthermore, the drain of the NMOS transistor 51 is connected to a node D1 of the latch circuit 32. The drain of the NMOS transistor 52 is connected to a node D2 of the latch circuit 32. The switch 40 is connected between the node D2 and a sensing node S and is turned on or off in response to a program control signal (PRGM). The column select circuit 12 includes NMOS transistors 81, 82. The sense amplifier circuit 14 includes PMOS transistors 91, 91 and NMOS transistors 93, 94. The data I/O operation of the data I/O circuit 10 constructed above will be described in short.
Upon data input, the data line discharge circuit 13 precharges a data I/O node DION with a ground voltage (VSS) level in response to a discharge control signal (DL_DIS). Thereafter, if column select signals (YA_DRV, YB_DRV) are enabled, the column select circuit 12 connects the data I/O node DION to the node D3 through an I/O line DIO. As a result, the node D3 becomes the ground voltage (VSS) level. At this time, if one of the data input signals (DI, nDI) is enabled, the latch circuit 32 latches data of logic “1” or “0”. Meanwhile, upon data output, the switch 60 connects the node D2 to the node D3 in response to the data output signal (PBDO). Furthermore, the column select circuit 12 connects the data I/O node DION to the node D3 through the I/O line DIO in response to the column select signals (YA_DRV, YB_DRV). Consequently, data stored in the latch circuit 32 is input to the sense amplifier circuit 14 consecutively through the node D3, the I/O line DIO, the column select circuit 12 and the data I/O node DION.
As described above, in the data I/O circuit 10 of the flash memory device in the related art, during the data I/O operation, input or output data are transmitted to the page buffer 11 or the sense amplifier circuit 14 through a single data I/O node DION. In this structure, a problem arises because the data I/O speed is decreased although the number of the whole transistors can be reduced. Furthermore, the page buffer 11 must include both the path (i.e., the data input circuit 50) through which data is input to the register circuit 30 and the path (i.e., the switch 60) through which data stored in the register circuit 30 is output. Accordingly, a problem arises because the page buffer 11 becomes bulky.